Modern integrated circuits are formed on the surfaces of semiconductor substrates, which are mostly silicon substrates. Semiconductor devices are isolated from each other by isolation structures formed at the surface of the respective semiconductor substrates. The isolation structures include field oxides and STI regions.
Field oxides are often formed using local oxidation of silicon (LOCOS). A typical formation process includes blanket forming a mask layer on a silicon substrate, and then patterning the mask layer to expose certain areas of the underlying silicon substrate. A thermal oxidation is then performed in an oxygen-containing environment to oxidize the exposed portions of the silicon substrate. The mask layer is then removed.
With the down-scaling of integrated circuits, STI regions are increasingly used as the isolation structures. FIGS. 1 and 2 illustrate intermediate stages in the formation of an STI region. First, an opening is formed in silicon substrate 10, for example, using etching. Oxide 12, preferably a silicon oxide, is filled into the opening, until the top surface of oxide 12 is higher than the top surface of silicon substrate 10. The opening has an aspect ratio, which equals to the ratio of depth D1 to width W1. The aspect ratio becomes increasingly greater when the integrated circuits are increasingly scaled down. For 40 nm technology and below, the aspect ratio will be greater, and sometimes far greater, than 7.0. For 32 nm technology, the aspect ratio may be greater than 10.
The increase in the aspect ratio causes problems. Referring to FIG. 1, in the filling of the opening, the high aspect ratio will adversely result in the formation of void 14, which is a result of the pre-mature sealing in the top region of the filling oxide 12. After a chemical mechanical polish (CMP) to remove excess oxide 12, STI region 16 is left in the opening, as is shown in FIG. 2. It is likely that void 14 is exposed after the CMP. In subsequent process steps, conductive materials such as polysilicon may be filled into the opening, causing the bridging, and even the shorting of integrated circuits in some circumstances.
Conventionally, oxide 12 is often formed using one of the two methods, high-density plasma (HDP) chemical vapor deposition and high aspect-ratio process (HARP). The HDP may fill gaps with aspect ratios less than about 6.0 without causing voids. The HARP may fill gaps with aspect ratios less than about 7.0 without causing voids. However, when the aspect ratios are close to 7.0, even if no voids are formed, the central portions of STI region 16 formed using the HARP are often weak. The weak portions may be damaged by the CMP processes or oxide wet dips, which in turn cause voids after the CMP or the oxide wet dips. When the aspect ratios further increase to greater than 7.0, voids start to appear even if the HARP is used. Accordingly, the existing gap-filling techniques can only fill gaps having aspect ratios less than 7.0 without causing voids. New gap-filling methods are thus needed.